I’m Andreas, a PhD researcher at KU Leuven (MICAS) focusing on AI/ML hardware acceleration.
My core passion is digital design, implementing fast and efficient algorithms targeting ASICs. Alongside a deep interest in general computing and computer architecture, I enjoy working across the entire stack. From analog IC sizing and data converters to RTL design, verification and hardware/software co-design. I love building complex systems from the ground up.
Skills#
- RTL & Digital Design: SystemVerilog, VHDL, ASIC synthesis, Yosys/LibreLane, Synopsys Design Compiler, Cadence Innovus
- Verification & Validation: Verilator, CocoTB, HW/SW co-design
- Analog & Mixed-Signal: IC design, gm/id sizing methodology, Cadence Virtuoso
- Programming: C, C++, Python
- Tools & Platforms: Xilinx Zynq, FPGAs, Linux, CI/CD, Git
Experience#
PhD Researcher - KU Leuven, MICAS | 2026-present
AI/ML hardware acceleration.
MSc Thesis Researcher (Intern) - imec, the Netherlands | 2026
End-to-end real-time compression system for high-density neural recording, with BCI applications.
Student Embedded Developer, IP Validation - STMicroelectronics | 2023-2025
Part-time. Testing, validation and low-level C/C++ programming of graphics IPs (DMA2D, GPU2D) on STM32 MCUs.